The invention relates generally to a method for optimizing the usage of flash memory systems, and more specifically, to a method for optimizing a read threshold voltage shift value in a NAND flash memory. The invention relates further to a related memory controller for optimizing a read threshold voltage shift value for a NAND flash memory, and a computer program product.
Enterprise storage capacity requirements are growing consistently. At the same time, prices for flash storage have decreased significantly in comparison to hard disk drive storage systems so that the demand for NAND flash-based memory has increased significantly. The cell density of such NAND flash memories is also ever-increasing and, the number of bits storable per cell is also increasing—e.g. TLC (triple level cell).
In NAND flash memories, cells are typically organized by word-lines and bit-lines into blocks. Currently, a block may have about 10,000,000 cells. The cells can be programmed as single-level cells (SLCs with one bit per cell) or multi-level cells (MLCs, at least two bits per cell). Using an SLC cell, as example, the threshold voltage determines whether a read-back voltage from a NAND cell is a 0 or a 1. If the read-back voltage is below the threshold voltage, it is decided that a logical “0” has been stored in the cell; if the read-back voltage is above the threshold voltage, it is decided that a logical “1” has been stored in the cell. However, if the number of levels in a single cell increases, a more precise threshold voltage determination is required for programming and read-back of data stored in the cells. This finer threshold voltage determination or setting makes MLCs prone to noise.
The raw bit error rate (RBER) of a flash memory block typically increases over time due to additional program and erase (P/E) cycling, charge leakage from retention and, read disturb errors. Typically, a flash memory block may be retired when a page in the block exhibits read errors that cannot be corrected by the error correction code (ECC) that is present at the flash memory controller.
The threshold voltage (VTH) is the voltage above which the cell conducts and depends on the amount of charge stored in the cell, read threshold voltage shifting, is used in block calibration to determine the optimal read threshold voltage shift values. In some prior art, read threshold voltage shift values are also known as threshold voltage shift (TVS) values. Block calibration is an effective method to reduce the number of read errors and, thus, to prolong endurance and retention for enterprise-level storage systems using NAND flash memories. Block calibration is normally periodically performed as part of an automated low-speed and low-priority background health check process, so as not to adversely impact user read or write operations. The improvement in endurance is achieved by setting the optimal threshold voltage shift (TVS) values at the granularity of groups of pages per block that result in minimizing the maximum raw bit error rate of each flash block.
This background setting of optimal TVS values relies on RBER rates observed during background reads and it stores a determined TVS value in metadata storage for a particular cell group. This basic background approach has been proven to work well in lateral (2-D) NAND flash memory devices. However, the recent proliferation of 3D NAND flash memory devices has introduced new distortion mechanisms that affect the RBER of flash memory pages and blocks in different ways than before. Notably, 3D flash memory exhibits an abrupt change in optimal voltage thresholds when switching from a P/E cycling phase to a retention phase, or due to a read disturb effect. The change in VTH is monotonically increasing with a number of P/E cycles—i.e., before retention or read disturb—that the block has seen, and is much more pronounced than in 2D flash memories.
As a result of the abrupt VTH change in 3D flash memories, the threshold-voltage shifting algorithm known in the art are not adequate any longer. Specifically, such algorithms are not flexible enough to track rapid changes in VTH due to retention or read disturb. Modifications to existing schemes are required in order to make also 3D flash memory reliable and durable. At the same time, it should be ensured that no unnecessary latencies and read bandwidth penalties are introduced.